IMPLEMENTATION OF MODIFIED BOOTH-WALLACE TREE MULTIPLIER IN FPGA

Abstract

The main purpose of this paper is to present the design and implementation of the Modified Booth Algorithm introduced by Andrew Donald Booth in 1950 and the Wallace tree structure is by an Australian Computer Scientist Chris Wallace in 1964. Combination of both algorithms is to implement a versatile algorithm widely used for digital signal processing application. Due to the highly demand on the fast microprocessors, designers come out with multiple techniques to produce a high speed multiplier. Modified Booth’s Algorithm have the advantages on faster multiplication process by reducing the generation of the partial products half of the number of bits of the multiplicand. The Wallace-tree multiplier itself giving a speed up in additional stage by reducing the adding partial products using the half adder and full adder instead of the long AND gate thus minimize the complexity of circuit. Combination of these two algorithms producing a new architecture of a high speed and low implementation area in one multiplier. This fulfil the requirement of high speed computer system nowadays. The algorithm was developed using Verilog HDL in Quartus II software and the result obtained from Modelsim-Altera then the design is implemented in FPGA DE2 Cyclone II to verify the result.